-------------------------------------------------------------------------------
-- Archivo: 			         vector.vhdl
-- Fecha de creación:            20/01/2011
-- Última fecha de modificación: 31/01/2011
-- Diseñador: 			         Jesús Pérez
-- Diseño: 			             vector
-- Propósito: 			         Vector de cuatro elementos para el archivo de registros
--                               vectorial
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity vector is
    port(
    	CLK_i 		    : in  std_logic;
    	WRITE_ENABLE0_i : in  std_logic;
    	WRITE_ENABLE1_i : in  std_logic;
    	WRITE_ENABLE2_i : in  std_logic;
    	WRITE_ENABLE3_i : in  std_logic;
    	DATA_i 	        : in  std_logic_vector (3 downto 0);
    	DATA0_o 	    : out std_logic_vector (3 downto 0);
    	DATA1_o         : out std_logic_vector (3 downto 0);
    	DATA2_o         : out std_logic_vector (3 downto 0);
    	DATA3_o         : out std_logic_vector (3 downto 0)
    );
end vector;

architecture structural of vector is

  component ffd
      port(
      	  D   : in  std_logic;
      	  E   : in  std_logic;
      	  CLK : in  std_logic;
          Q   : out std_logic      
    );
  end component;

begin

    FFD0 : ffd port map(
        D   => DATA_i(0),
        E   => WRITE_ENABLE0_i,
        CLK => CLK_i,
        Q   => DATA0_o(0)
    );

    FFD1 : ffd port map(
        D   => DATA_i(1),
        E   => WRITE_ENABLE0_i,
        CLK => CLK_i,
        Q   => DATA0_o(1)
    );
  
    FFD2 : ffd port map(
        D   => DATA_i(2),
        E   => WRITE_ENABLE0_i,
        CLK => CLK_i,
        Q   => DATA0_o(2)
    );
  
    FFD3 : ffd port map(
        D   => DATA_i(3),
        E   => WRITE_ENABLE0_i,
        CLK => CLK_i,
        Q   => DATA0_o(3)
    );

    FFD4 : ffd port map(
        D   => DATA_i(0),
        E   => WRITE_ENABLE1_i,
        CLK => CLK_i,
        Q   => DATA1_o(0)
    );

    FFD5 : ffd port map(
        D   => DATA_i(1),
        E   => WRITE_ENABLE1_i,
        CLK => CLK_i,
        Q   => DATA1_o(1)
    );
  
    FFD6 : ffd port map(
        D   => DATA_i(2),
        E   => WRITE_ENABLE1_i,
        CLK => CLK_i,
        Q   => DATA1_o(2)
    );
  
    FFD7 : ffd port map(
        D   => DATA_i(3),
        E   => WRITE_ENABLE1_i,
        CLK => CLK_i,
        Q   => DATA1_o(3)
    );

    FFD8 : ffd port map(
        D   => DATA_i(0),
        E   => WRITE_ENABLE2_i,
        CLK => CLK_i,
        Q   => DATA2_o(0)
    ); 

    FFD9 : ffd port map(
        D   => DATA_i(1),
        E   => WRITE_ENABLE2_i,
        CLK => CLK_i,
        Q   => DATA2_o(1)
    );
  
    FFD10 : ffd port map(
        D   => DATA_i(2),
        E   => WRITE_ENABLE2_i,
        CLK => CLK_i,
        Q   => DATA2_o(2)
    );
  
    FFD11 : ffd port map(
        D   => DATA_i(3),
        E   => WRITE_ENABLE2_i,
        CLK => CLK_i,
        Q   => DATA2_o(3)
    );
  
    FFD12 : ffd port map(
        D   => DATA_i(0),
        E   => WRITE_ENABLE3_i,
        CLK => CLK_i,
        Q   => DATA3_o(0)
    );

    FFD13 : ffd port map(
        D   => DATA_i(1),
        E   => WRITE_ENABLE3_i,
        CLK => CLK_i,
        Q   => DATA3_o(1)
    );
  
    FFD14 : ffd port map(
        D   => DATA_i(2),
        E   => WRITE_ENABLE3_i,
        CLK => CLK_i,
        Q   => DATA3_o(2)
    );
  
    FFD15 : ffd port map(
        D   => DATA_i(3),
        E   => WRITE_ENABLE3_i,
        CLK => CLK_i,
        Q   => DATA3_o(3)
    );
  
end structural;

